1. Field of the Invention
The present invention relates to a semiconductor memory having electrically erasable, nonvolatile split gate memory cells generally called MNOS memory cells or MONOS memory cells.
2. Description of the Related Art
An electrically erasable, nonvolatile split gate memory cell generally called a MNOS memory cell or a MONOS memory cell has two gate electrodes, i.e., an address gate electrode and a memory gate electrode. A voltage to be applied to the memory gate to turn on the integral transistor of the memory cell, i.e., a threshold voltage, changes depending on whether electrons are injected (write) into a predetermined layer of the memory gate or electrons are emitted (erase) from the predetermined layer. A digital value "0" is stored in the memory cell for writing or a digital value "1" is stored in the memory cell for erasing. In read operation, it is recognized whether the memory cell has been written or in erased, namely, whether the contents of the memory cell is "0" or "1", through the detection of the threshold voltage.
FIG. 6 is a circuit diagram of a portion of a semiconductor memory employing such nonvolatile split gate memory cells and FIG. 7 is a plan view of a semiconductor chip, showing the portion of the semiconductor memory shown in FIG. 6. In FIGS. 6 and 7, like or corresponding parts are denoted by the same reference characters.
Shown in FIGS. 6 and 7 are four memory cells 10, 20, 30 and 40. The respective drain electrodes 11 and 31 of the memory cells 10 and 30 are connected to a bit line Bi, namely, a vertical line, and the respective drain electrodes 21 and 41 of the memory cells 20 and 40 are connected to a bit line Bi+1. The respective source electrodes 12, 22, 32 and 42 of the memory cells 10, 20, 30 and 20 are grounded. The respective address gate electrodes 13 and 23 of the memory cells 10 and 20 are connected to an address gate line X1, and the respective memory gate electrodes 14 and 24 of the memory cells 10 and 20 are connected to a memory gate line W1. Similarly, the respective address gate electrodes 33 and 43 of the memory cells 30 and 40 are connected to an address gate line X2 and the respective memory gate electrodes of the memory cells 30 and 40 are connected to a memory gate line W2.
When writing data on the memory cell 10 of the semiconductor memory, a voltage of, for example, 0 V is applied to the memory gate line W1, and the bit line Bi and the substrate are grounded. When erasing the memory cell 10, the memory gate line W1 is grounded and a voltage of 9 V is applied to the bit line Bi. When reading the contents of 1 the memory cell 10, a predetermined positive voltage is applied to the address gate line X1, and the bit line Bi is connected to a current sense amplifier, not shown, to decide whether the contents of the memory cell 10 is "0" or "1" by detecting whether any current flows from the drain electrode 11 of the memory cell 10 to the source electrode 12 of the same (ON state) or whether no current flows from the drain electrode 11 to the source electrode 12 (OFF state).
The number of repetition of rewrite operation, i.e., erase and write operation, possible with the nonvolatile split gate memory cell, such as a MONOS memory cell, is on the order of 107, which is about 100 times the number of repetition of rewrite operation with a stacked gate memory cell having two superposed gates.
Although the possibility of repeating rewrite operation such a large number of times is a significant advantage of the nonvolatile split gate memory cell, the area of the nonvolatile split gate memory cell is greater than that of the stacked gate memory cell and hence the degree of integration of a semiconductor memory comprising nonvolatile split gate memory cells is reduced accordingly, and the size of a chip carrying a semiconductor memory comprising nonvolatile split gate memory cells is greater than that of a chip carrying a semiconductor memory comprising stacked gate memory cells and having a storage capacity equal to the former semiconductor memory, because the address gate electrode and the memory gate electrode of the nonvolatile split gate memory cell are arranged side by side in a plane and the area of each memory cell enclosed by alternate long and short dash lines in FIG. 7 is about 17.2 .mu.m2 if the configuration shown in FIG. 7 is designed on the basis of a design rule of, for example, 1 .mu.m, which is greater than the area of a stacked gate memory cell designed on the basis of the same design rule by about 20%.
Memory cells of a known semiconductor memory of an X-configuration, such as a ROM of an X-configuration, are arranged in a layout capable of increasing the degree of integration.
FIG. 8 is a circuit diagram showing a portion of such a ROM of an X-configuration.
Three bit lines Bi-1, Bi and Bi+1 among a plurality of bit lines, and four memory cells 110, 120, 130 and 140 disposed between the adjacent bit lines among a plurality of memory cells are shown in FIG. 8, in which the bit lines are extended vertically. The memory cells 110 and 120 are arranged on a memory cell line extending between the upper left-hand point and a lower right-hand point, and the memory cells 120 and 130 arranged on a memory cell line extending between an upper right-hand point and a lower left-hand point.
The memory cells 110, 120, 130 and 140 have two source/drain electrodes 111 and 112, two source/drain electrodes 121 and 122, two source/drain electrodes 131 and 132, and two source/drain electrodes 141 and 142, respectively. The source/drain electrodes 112, 122, 131 and 141 are connected to a predetermined point 160 on the bit line Bi. The respective source/drain electrodes 111 and 132 of the memory cells 110 and 130 are connected to predetermined points on the bit line Bi-1, respectively. The respective source/drain electrodes 121 and 142 of the memory cells 120 and 140 are connected to predetermined points on the bit line Bi+1, respectively. The respective gate electrodes 113 and 123 of the memory cells 110 and 120 are connected to a gate line W1 horizontally extending in FIG. 8, and the respective gate electrodes 133 and 143 of the memory cells 130 and 140 are connected to a gate line W2.
In the ROM, "1" is stored in, for example, the memory cell 110 when a line 115 connecting the memory cell 110 to the bit line Bi-1 is equivalently broken or "0" is stored in the memory cell 110 when the line 115 is not equivalently broken. For example, in reading information stored in the memory cell 110, "1" is read from the memory cell 110 if no current flows through the memory cell 110 when the bit line Bi-1 is grounded, the bit line Bi is connected to a current sense amplifier and a predetermined positive voltage is applied to the gate line W1. For example, in reading information stored in the memory cell 120, "0" is read from the memory cell 120 if a current flows through the memory cell 120 when the bit line Bi is grounded, the bit line Bi+1 is connected to a current sense amplifier and a predetermined positive voltage is applied to the gate line W1.
In forming a ROM having memory cells each having a single gate, the memory cells can be arranged in a high density on a semiconductor chip to increase the degree of integration by arranging the memory cells in an X-configuration. However, it is difficult to arrange split gate memory cells in an X-configuration because of the following reasons.
FIG. 9 is a circuit diagram of a portion of a semiconductor memory comprising split gate memory cells arranged in an X-configuration, in which three bit lines Bi-1, Bi and Bi+1 among a plurality of bit lines, and four memory cells 210, 220, 230 and 240 among a plurality of memory cells are shown. The memory cells 210, 220, 230 and 240 are disposed between the adjacent bit line, the memory cells 210 and 240 are arranged on a memory cell line extending between an upper left-hand point and a lower right-hand point, and the memory cells 220 and 230 are arranged on a memory cell line extending between an upper right-hand point and a lower left-hand point.
The memory cells 210, 220, 230 and 240 have two source/drain electrodes 211 and 212, two source/drain electrodes 221 and 222, two source/drain electrodes 231 and 232, and two source/drain electrodes 241 and 242, respectively. The source/drain electrodes 212, 222, 231 and 241 are connected to a predetermined point 260 on the bit line Bi. The respective source/drain electrodes 211 and 232 of the memory cells 210 and 230 are connected, respectively, to predetermined points on the bit line Bi-1, the respective source/drain electrodes 221 and 242 of the memory cells 220 and 240 are connected, respectively, to predetermined points on the bit line Bi+1. The respective address gate electrodes 213 and 223 of the memory cells 210 and 220 are connected to an address gate line X1, the respective memory gate electrodes 214 and 224 of the memory cells 210 and 220 are connected to a memory gate line W1, the respective address gate electrodes 233 and 243 of the memory cells 230 and 220 are connected to an address gate line X2, and the respective memory gate electrodes 234 and 244 of the memory cells 230 and 340 are connected to a memory gate line W2.
In writing data on, for example, the memory cell 230, a voltage of, for example, 9 V is applied to the memory gate line W2 and the bit line Bi is grounded to inject electrons (write) into the memory gate electrode 234 of the memory cell 230. Since the respective memory gate electrodes 234 and 244 of the memory cells 230 and 240 are connected to the memory gate line W2, the voltage of 9 V is applied simultaneously to both the memory gate electrodes 232 and 244. Since the respective source/drain electrodes 231 and 241 of the memory cells 230 and 240 are connected to the bit line Bi, both the source/drain electrode 231 of the memory cell 230 and the source/drain electrode 241 of the memory cell 240 goes 0 V when the bit line Bi is grounded and, consequently, the data is written on both the memory cells 230 and 240. Thus, the respective states (write state and erase state) of the two memory cells 230 and 240 cannot be individually controlled.
The degree of integration is dependent on the size of the memory cells as well as on the layout of the memory cells. The effect of reduction in size of memory cells will be described hereinafter.
FIG. 10 is a circuit diagram of a portion of a semiconductor memory comprising the foregoing nonvolatile split gate memory cells (Takaaki Nozaki, et al., "A 1 Mb EEPROM with MONOS Memory Cell for Semiconductor Disk Application", IEEE Journal of Solid-state Circuits, Vol. 26, No. 4, April 1991).
In FIG. 10, four memory cells 410, 420, 430 and 440 among a plurality of memory cells. The respective address gate electrodes 411 and 421 of the memory cells 410 and 420 are connected to an address gate line X11, the respective memory gate electrodes 412 and 422 of the memory cells 410 and 420 are connected to a memory gate line W11, the respective drain electrodes 413 and 423 of the memory cells 40 and 420 are connected, respectively, to bit lines B11 and B21, and the memory cells 410 and 420 have a common source electrode 402. The source electrode 402 is connected electrically to a substrate 401 as represented by a line CS/PW. The memory cells 430 and 440 are similar in construction to the memory cells 410 and 420. The respective address gate electrodes 431 and 441 of the memory cells 430 and 440 are connected to an address gate line X21, the memory gate electrodes 432 and 442 of the memory cells 430 and 440 are connected to a memory gate line W21, and the respective drain electrodes 433 and 434 of the memory cells 430 and 440 are connected, respectively, to bit lines B11 and B21. The memory cells 430 and 440 have a common source electrode 403 connected to the line CS/PW.
When writing data on, erasing data stored in or reading data from the memory cell 410, voltages tabulated in Table 1 are applied to the lines X11, X21, W11, W21, B11, B21 and CS/PW.
TABLE 1 ______________________________________ Lines X11 X21 W11 W2 B11 B21 CS/PW ______________________________________ Write mode -4 -4 5 -4 -4 5 -4 Erase mode -4 -4 -4 -4 5 5 5 Read mode 5 0 0 0 Sense Open 0 amp. ______________________________________
The operation of the prior art semiconductor memory in the write mode, in which problems reside, will be described hereinafter.
In the write mode, the memory gate line W11 is at 5 V and the bit line B11 is at -4 V. Therefore, the voltage across the memory electrode 412 of the memory cell 410 and a layer 412' facing the memory electrode 412 is 9 V, and electrons ape injected from the substrate 401 into the memory gate electrode 412 for writing; in the meantime a voltage of 5 V is applied to the memory gate electrode 422 of the memory cell 420, and a voltage of -4 V is applied to a layer 422' facing the memory gate electrode 422 if the memory cell 420 has been written, or a voltage of 5 V is applied to the layer 422' if the memory cell 420 has been erased. If the memory cell 420 has been written, the voltage applied across the memory gate electrode 422 and the layer 422'9 V and data is written again on the memory cell 420. Since the memory cell 420 has been written, no problem arises in writing data in the memory cell 420. If the memory cell 420 has been erased, the voltage across the memory gate electrode 422 and the layer 422' is 0 V, and neither writing nor erasing is performed. Similarly, not problems arises in writing data on or erasing data written on the memory cells 430 and 440.
There is no problem in writing data on or erasing data written on the memory cell 420 in the write mode. However, a voltage of 9 V is applied across the drain electrode 423 (5 V) and the source electrode 402 (-4 V).
Recently, the degree of integration of integrated circuits has been progressively increased and the microminiaturization of integrated circuits has been progressively advanced. For example, the application of design rules of 0.8 .mu.m and 0.5 .mu.m to designing integrated circuits has been tried.
In writing data in memory cells, a voltage on the order of 9 V must be applied across the memory cells regardless of the size of the memory cells. The withstand voltage across the drain and source of the memory cell decreases with the miniaturization of the memory cell, and a design rule of 1.0 .mu.m is substantially the smallest possible design rule. If a voltage higher than the withstand voltage is applied across the drain and source of the memory cell, punch-through occurs and a current flows through the source and the drain regardless the gate voltage. Thus, the reduction in the withstand voltage across the drain and source of the memory cell is a barrier to the miniaturization of the memory cell. References will be made to the life of MNOS memory cells and MONOS memory cells.
FIG. 11 is a graph showing the dependence of threshold voltages for a MNOS memory cell and a MONOS memory cell on write time and erase time. If the write time and the erase time is 1 msec, the threshold voltage for writing is about +2 V and the threshold voltage for erasing is about -2 V.
When reading data from the memory cell, the difference (memory window) between the threshold voltage for a write state (referred to as "state 0") where electrons are injected into the memory cell and the threshold voltage for an erase state (referred to as "state 1") where electrons are extracted from the memory cell is determined to discriminate between the state 0 and the state 1; that is, for example, if a voltage of, for example, 0 V corresponding to the middle voltage between the threshold voltage of, for example, 2 V for the state 0 and that of, for example, -2 V for the state 1 is applied to the gate, the potential 0 V of the gate is lower than the threshold voltage +2 V for the state 0 in the state 0 and the memory cell is in an OFF state, and the gate voltage 0 V is higher than the threshold voltage -2 V for the state 1 in the state 1 and the memory cell is in an ON state. Thus, the contents of the memory cell, i.e., "0" or "1" is detected through the detection of the potential of the read line or the current flowing through the read line.
The threshold voltages for the memory cells change with time and the mode of change of the threshold voltages is dependent on the number of times of repetition of writing and erasing.
FIG. 12 is a graph showing the charge holding characteristics of a MNOS memory cell after predetermined numbers of write-erase cycles, namely, one write-erase cycle, 105 write-erase cycles, 106 write-erase cycles and 107 write-erase cycles. As is obvious from FIG. 12, the threshold voltage for writing decreases with time while the threshold voltage for erasing increases with time, so that the difference between the threshold voltage for writing and that for the erasing decreases. The respective modes of the threshold voltage for writing and the threshold voltage for erasing are dependent on the numbers of repetition of write cycles and erase cycles.
When the threshold voltage for writing or erasing is in a discrimination unable range shown in FIG. 11, it is impossible to discriminate between the state 0 and the state 1. Accordingly, time in which the threshold voltage for the writing decreases or the threshold voltage for erasing increases to a voltage within the discrimination unable range is the life of the memory cell. The discrimination unable range is dependent principally on the circuit configuration of the read system. For example, in the case of the memory cell having the threshold voltage characteristics shown in FIG. 11, if rewrite cycle is repeated 107 times, the threshold voltage for erasing increases to a voltage within the discrimination unable range in about 106 sec (about eleven days), which is the life of the memory cell. The change of the threshold voltage of the MONOS memory cell is similar to that of the threshold voltage of the MNOS memory cell. For example, the life of the MONOS memory cell is about ten years when rewrite cycle is repeated 107 times.
It is one of the important problems with erasable nonvolatile memory cells, such as MNOS memory cells and MONOS memory cells, to increase the number of possible rewrite cycles without shortening the life.